收藏本站
CS5460A
CRDY
EDIR
EOUT
DRDY
Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate,
which is usually 4 kHz.
Set whenever the EOUT bit asserted (see below) if the accumulated energy is negative.
Indicates that enough positive/negative energy has been reached within the internal EOUT En-
ergy Accumulation Register (not accessible to user) to mandate the generation of one or more
pulses on the EOUT pin (if enabled, see Configuration Register ). The energy flow may indicate
negative energy or positive energy. (The sign is determined by the EDIR bit, described above).
This EOUT bit is cleared automatically when the energy rate drops below the level that produc-
es a 4 kHz EOUT pin rate. The bit can also be cleared by writing to the Status Register. This
status bit is set with a maximum frequency of 4 kHz (when MCLK/K is 4.096 MHz). When
MCLK/K is not equal to 4.096 MHz, the user should scale the pulse-rate by a factor of
4.096 MHz / (MCLK/K) to get the actual pulse-rate.
Data Ready. When running in ’single computation cycle’ or ’continuous computation cycles’
data acquisition modes, this bit will indicate the end of computation cycles. When running cali-
brations, this bit indicates that the calibration sequence has completed, and the results have
been stored in the offset or gain registers.
5.12 Control Register
Address: 28
23
Res
15
Res
7
Res
22
Res
14
Res
6
MECH
21
Res
13
Res
5
Res
20
Res
12
Res
4
INTL
19
Res
11
Res
3
SYNC
18
Res
10
Res
2
NOCPU
17
Res
9
Res
1
NOOSC
16
Res
8
STOP
0
STEP
Default** = 0x000000
50
STOP
Res
MECH
INTL
SYNC
NOCPU
NOOSC
STEP
1 = used to terminate the new EEBOOT sequence.
Reserved. These bits must be set to zero.
1 = widens EOUT and EDIR pulses for mechanical counters.
1 = converts the INT output to open drain configuration.
1 = forces internal A/D converter clock to synchronize to the initiation of a conversion command.
1 = converts the CPUCLK output to a one-bit output port. Reduces power consumption.
1 = saves power by disabling the crystal oscillator for external drive.
1 = enables stepper-motor signals on the EOUT/EDIR pins.
DS487F5
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
CDB5461AU BOARD EVAL & SOFTWARE CS5461A
CDB5466U BOARD EVAL & SOFTWARE CS5466 ADC
CDB5467U BOARD EVAL FOR CS5467 ADC
CDB5560-2 DEV BOARD FOR CS5560 W/SE INPUT
CDB5571-2 DEV BOARD FOR CS5571 W/SE INPUT
CDB8422 BOARD EVAL FOR CS8422 RCVR
CDB8952T BOARD EVAL FOR CS8952
CDCE906-706PERFEVM EVAL MOD PERFORMANCE CDCE906/706
相关代理商/技术参数
CDB5460AU-Z 制造商:Cirrus Logic 功能描述:PB-FREEEVAL BOARD FOR CS5460 - Bulk
CDB5461 制造商:Cirrus Logic 功能描述:EVAL BD FOR CS5461 - Bulk
CDB5461A 功能描述:EVAL BOARD FOR CS5461 RoHS:否 类别:编程器，开发系统 >> 过时/停产零件编号 系列:- 标准包装:1 系列:- 类型:MCU 适用于相关产品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、缆线、软件、数据表和用户手册 其它名称:520-1035
CDB5461AU 功能描述:数据转换 IC 开发工具 Eval Bd Sngl-Phase Pow/Energy RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V
CDB5461AU-Z 制造商:Cirrus Logic 功能描述:PB-FREEEVAL BOARD FOR CS5461 WITH USB - Bulk
CDB5462 制造商:Cirrus Logic 功能描述:EVAL BOARD FOR CS5462 - Bulk
CDB5463U 功能描述:数据转换 IC 开发工具 Eval Bd Sngl-Phase Pow/Energy RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V
CDB5463U-Z 功能描述:EVAL BOARD USB FOR CS5463 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件